Current television receivers receive a single channel through a single tuner. The evolving market for data and programming services will demand that receivers have the capability of multi-channel tuning.
A block diagram of a conventional single-channel cable TV receiver is illustrated in FIG. 1. The composite TV signal is received at the input of the receiver and amplified to the correct level with a low-noise-amplifier and variable gain amplifier (LNA/VGA) 102. A programmable band selection filter 104 can potentially make a pre-selection on the composite signal to limit its bandwidth and easy the subsequent signal processing operations.
A specific TV channel is selected with the use of a frequency synthesizer 106 that tunes to the corresponding channel frequency. By multiplying the synthesized frequency reference signal and the received signal together with the aid of the mixer circuit 108, the wanted channel is down-converted (its carrier frequency is shifted) to a convenient frequency and then all other channels left and right of it in the frequency domain are removed with use of filters 110 and 112. The remaining signal of the wanted channel is then amplified 114 further to exploit optimally the ADC 116 input range, which digitizes it. As a result of the predominantly analog signal pre-processing the signal that the ADC 116 usually samples has very low frequency of operation leading to very relaxed ADC requirements. Channel decoder 118 produces a single transport stream containing the desired signal.
The block consisting of all circuits in FIG. 1 from LNA/VGA to the input of the ADC 116 is usually called a “tuner.” The tuner realizes the complete channel selection process in the analog domain and it delivers at its output a single channel at a very convenient frequency for further baseband processing. The tuner circuit has reached a very high level of design sophistication to deal with several circuit realization imperfections, such as mismatch between I/Q paths, mixer down-conversion inaccuracies, etc. In most cases, the tuner is realized in a Silicon Bipolar or BiCMOS process in order to reach the RF performance required, but which restricts the tuner from being integrated into a larger SoC system. The output of the tuner remains an analog signal since the ADC is usually realized in CMOS and placed in the decoder side.
The remaining circuitry (the ADC, the baseband processor for further digital signal processing, carrier recovery, channel decoding, source decoding, etc.) is usually a separate IC and it is called the baseband IC.
Existing receiver architectures based on the concept shown in FIG. 1 are not able to satisfy properly the need for multi-channel reception. The conventional approach would be to use many single channel tuners in parallel connected to the same input signal source to make a multi-channel tuner. This approach, however, faces major limitations related to complexity of system implementation, signal quality, and cost effectiveness. As the number of simultaneously required streams/channels goes beyond two, the conventional approach becomes completely impractical.
Implementing a truly multi-channel receiver with conventional approaches requires the input signal to be supplied to all individual single channel receivers. To achieve this, RF signal replicating means such as power splitters, RF signal buffers, etc. are used. This allows routing the RF input to the main receiver, and the replica RF signal to a second receiver. However, every time the RF input signal is replicated its quality degrades significantly with no possibility to recover the quality back.
Another draw back of building a multi-channel receiver from conventional components is that the channel selection process requires independent frequency synthesis means per tuner used. For 16 channels, 16 independent frequency synthesizers and PLL's are needed each being able to realize any channel frequency among approximately 100 in the TV band. Such an approach is clearly impractical.
Conventional I/Q receiver architectures are significantly affected by the well-known image rejection problem rising from mismatches in I and Q paths and their associated mixers. Further implementation limitations in I/Q mixers are also characteristics of this approach. For example, phase noise in the frequency translation stage (the mixer) is one of the dominant noise contaminating mechanisms of the conventional receiver architecture.
An alternative approach is to use a block receiver. This uses effectively the same architecture shown in FIG. 1. However, instead of filtering out everything but the single wanted channel, a block of channels (e.g. 5-10 TV channels) is down-converted to a convenient low frequency. After this frequency translation, all other TV signal components are removed with the aid of filters, and the resulting signal is amplified and then delivered at the output of the tuner. The block of TV channels is subsequently digitized with an ADC, faster than that required by the single channel tuner since now it needs to digitize a block of TV channels together. It becomes possible in this way to provide a few channels simultaneously at the output of the tuner.
In August of 2006, Cable Labs, Inc. issued “Data Over Cable Service Interface Specification (DOCSIS) 3.0.” DOCSIS 3.0 data reception and channel binding, both of which require the simultaneous reception of at least 4 channels placed not further than 60 MHz apart from each other. The block tuner described above enables DOCSIS 3.0, but does not enable unrestricted multi-channel functionality. For example, the simultaneously received number of channels is small and there is no freedom from a user's perspective to select (or combine together for faster data reception) many/any channels freely out of the full cable TV band. The latter usually consist of up to 100 channels between 50-1000 MHz. The resulting situation is that separate receivers are required to receive both TV and DOCSIS (data) channels without the reception of one restricting the basic functionality of the other. Several implementation limitations appear as well. For example, for a 4-channel system the tuner IC needs to output four clean analog baseband output signals to the decoder IC. The block receiver approach is clearly not the best for interference reasons.
Direct sampling of cable band signals for television reception under the DOCSIS standards requires sampling and quantization of signals with GHz bandwidth with proportionally larger sampling rates and with very high dynamic range (e.g. 50-70 dB). A second major issue is the capability to process digital signals with very high data rates.
For example, assume that the input signal is a cable TV signal consisting of multiple channels of 6 MHz each bundled together between 50-1000 MHz. The result of digitization of this signal is a data rate of 20-80 Gbits/sec (10-12 b resolution at 2 GS/sec rate at minimum is needed from the ADC). The steepness of the digital filters required in order to isolate one 6 MHz channel out of 100 TV channels in the 1 GHz band at the aforementioned rate complicates the situation significantly. Conventional digital signal processing selectivity techniques are not able to deal with these issues with area and power efficiency at reasonable levels for commercial use. The resulting on-chip interference generated by the activity of such a filter is also a great concern for the proper operation of the ADC and RF amplifier.
The development of discrete high-speed ADC chips and discrete multi-channel selection filtering chips does not solve the overarching problem of managing timing issues resulting from the high sample rates required for a multi-channel receiver. The amount of digital data that needs to be transported from the ADC block to the digital filter in a true multi-channel receiver is on the order of 20-80 Gb/s, or more. Data transportation at these speeds is extremely difficult, especially when it comes to transport from one IC to another. In addition, transporting data at such rates from one IC to another requires awareness of electromagnetic compatibility (EMC) and related interference issues that can easily impair the ADC performance. The input signal of the ADC is practically the input of the receiver, therefore very weak and easily susceptible to signal degradation. Use of low swing differential signaling standards (e.g. LVDS) could reduce EMC relate issues, but not to an acceptable level due to the extreme high data rate (thus, very high number of high speed signals) to convey the real data stream of 20-80 Gbits/sec from IC to IC. Additionally, while it might seem feasible to use on-chip memory to alleviate the EMC related issues of high-speed IC-to-IC transmission, memory usage raises technical issues of its own and is not feasible in applications where real time streaming is desired.
Clocking of the operations between ADC and digital filter is also a point of concern. A discrete filter chip connected to a full rate ADC (12 b 2 GS/sec) must capture these data synchronously at 2 GHz. One approach is to use a central 2 GHz sync clock distributed between the two IC's. Alternatively, additional PLL's can be use both supplied by the same crystal oscillator. In both cases, the complexity is significantly higher because the circuits that must be synchronized may be 1-10 cm's apart.
What is needed, therefore, is a single IC receiver able to provide unrestricted multi-channel functionality.
In an embodiment, a multi-channel receiver comprises an analog-to-digital converter (ADC) configured to convert using a sampling rate S an analog signal z which resides in a frequency band B Hz to a digital signal x, wherein digital signal x is representative of analog signal z, and a multi-band selector circuit configured to receive the digital signal x and to map the digital signal x into M time domain sub-signals x1 . . . xM, wherein each sub-signal represents in a time domain a frequency domain content of digital signal x, wherein each sub-signal resides in a sub-range of band B, wherein each frequency component of digital signal x is represented at least in one of the sub-signals x1 . . . xM in its original form, and wherein each of the sub-signals x1 . . . xM has a sampling rate less than S.
In another embodiment, the multi-band selector is further configured to map the digital signal x into M time domain sub-signals x1 . . . xM hierarchically.
In yet another embodiment, the multi-channel receiver comprises at least one channel selector connected to the output of the multi-band selector. The channel selector is configured to select at least one channel out of any sub-signals x1 . . . xM.
In still another embodiment, the multi-band selector circuit comprises at least two signal branches. In this embodiment, at least one branch is a filter-bank and at least one branch is a digital frequency translator connected to another filter-bank. The sub-ranges may overlap. By way of illustration and not as a limitation, the sub-ranges overlap at least by an amount equal to a channel width of the at least one channel selector.
In an embodiment, the multi-band selector circuit comprises a plurality of processing branches corresponding to respective phases and an adder for adding branch signals from the processing branches. At least two of the plurality of processing branches comprise a sub-sampler for sub-sampling sample values of the input signal at the phase corresponding to the branch, a block realizing sign inversion of the sub-sampled values cyclically, a filter comprising a first FIR filter. The filter is applied alternately to sets of sub-samples from the sub-sampler at even sub-sample positions and to sets at odd sub-sample positions. The branches further comprise a second FIR filter applied to further sets of sub-samples at odd and even sub-sample positions from the sub-sampler when the first FIR filter is applied to the sets of sub-samples at even and odd sub-sample positions respectively. The multi-band selector further comprises a combiner for combining output samples from the first and second FIR filter into the branch signals of the branch according to a combination pattern that changes cyclically as a function of sub-sample position and is responsive to a phase of the branch.
In another embodiment, the ADC is selected from the group consisting of a time-interleaved ADC and a partitioned time-interleaved ADC.
In still another embodiment, the ADC is a partition time-interleaved ADC comprising a main signal input for inputting an analog signal into the circuit, a front end circuitry comprising a plurality (N) of sampling units each having a signal input and a signal output, wherein the signal input of each of the sampling units is connected to said main signal input, a backend circuitry comprising a plurality of demultiplexers each having a signal input and a group (K) of signal outputs, and a plurality (N) of groups (K) of ADC units each ADC unit having a signal input and a data output. In this embodiment, the signal output of each sampling unit is connected to the signal input of one demultiplexer of said plurality of demultiplexers, and the signal outputs of each demultiplexer are connected to the signal inputs of the ADC units of one group of ADC units. Additionally, the main signal input is configured to feed the analog signal to said plurality (N) of sampling units using time interleaving, and the demultiplexers are configured to feed the sampled signal to said plurality (N) of groups of ADC units using time interleaving.
In an embodiment at least one demultiplexer of the ADC comprises an additional signal processing circuit. By way of illustration and not as a limitation, the additional signal processing circuit may be a buffer, a follower, and an amplifier.
In another embodiment, at least one ADC unit of the plurality of ADC units is configured to resample the sampled signal output by the respective sampling unit.
In yet another embodiment, the ADC comprises a clock input configured to provide a first plurality of clock signals clocking the plurality of sampling units and a second plurality of clock signals clocking the plurality of groups of ADC units. In an alternate embodiment, the ADC comprises a clock input configured to provide a first plurality of clock signals clocking the plurality of sampling units and a second plurality of clock signals clocking the plurality of groups of ADC units.
In an embodiment, at least one signal conditioning unit of the ADC is arranged between the main signal input and the signal inputs of the sampling units. By way of illustration and not as a limitation, the at least one signal conditioning unit may be a copier and/or a buffer.
In still another embodiment, the ADC further comprises a data recombination unit configured to recombine the data being output by the data outputs of the ADC units of the plurality of groups of ADC units so as to generate a one-dimensional digital data stream.
In an embodiment, the combiner of a first one of the at least two of the plurality of branches is configured to form complex branch signals, a real part of the complex branch signal being formed from an output signal of the first and second FIR filter of the first one of the branches alternatingly, and an imaginary part of the complex branch signal being formed from the output signal of the second and first FIR filter of the first one of the branches when the real part is formed from the output signal of the first and second FIR filter respectively. The combiner of a second one of the at least two of the plurality of branches is configured to form the real and imaginary parts of the complex branch signal by summing and subtracting the output signal of the first and second FIR filter of the second one of the branches.
In still another embodiment, the multi-channel receiver further comprising one more channel decoders, wherein a channel decoder receives a channel signal from the channel selector. In yet another embodiment, the multi-channel receiver further comprising one or more source decoders, wherein a source decoder receives an output from a channel decoder.
In an embodiment, the multi-channel receiver further comprises a signal processing unit, wherein the signal processing unit comprises an RF pre-processing unit, wherein the RF pre-processing unit receives a source signal and provides a processed signal to the ADC. By way of illustration and not as a limitation, the RF pre-processing unit comprises at least one of a filter, a low-noise amplifier, a variable gain amplifier and an equalizer.